含1个数统计电路设计

含“1”系统的电路控制ASM图：

1）控制器设计： 代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity one isport(cp,start,reset,n,x:in std_logic;    cp1,cp2,o:out std_logic);end one;architecture a of one istype state is(s0,s1,s2);signal current_st,next_st :state;begin process(cp,reset)beginif reset='1' then current_st<=s0;elsif cp'event and cp='0' then    current_st<=next_st;     end if;    end process; process(start,current_st,n,cp,x)begin    case  current_st is                           when s0=>o<='0';                       if start='1'then next_st<=s1; cp1<='0';cp2<='0';o<='1';                       else next_st<=s0;cp1<='0';cp2<='0';                        end if;              when s1=>o<='0';next_st<=s2;cp1<='0';                       if x='1' then cp2<=cp;                       else  cp2<='0';              end if;              when s2=>                       if x='0' and n='0' then next_st<=s2;cp1<=cp;cp2<='0';                       elsif x='0' and n='1' then next_st<=s0;cp1<=cp;cp2<='0';                       elsif x='1' and n='0'  then next_st<=s2;cp1<=cp;cp2<=cp;                       elsif x='1' and n='1'  then next_st<=s0;cp1<=cp;cp2<=cp;                       else next_st<=s2;cp1<='0';cp2<='0';                       end if;                            when others=>next_st<=s0;cp1<='0';cp2<='0';o<='0';  end case;  end process;  end a;

生成的图形模块如图：

整体电路的设计图：

系统测试  状态机模型：

仿真结果